1. Field of the Invention
The present invention relates to a layout data creation device for transistor and a semiconductor device.
2. Description of Related Art
Conventionally, as a high-performance and high-density integrated circuit is developed, it is important to optimize the performance and area of transistor cells that make up the integrated circuit. In particular, the load capacity, drive capability, and area of transistors have a great impact on the performance and area of a cell that is made up of the transistors.
Improvements of integration degree of semiconductor memory devices have largely been achieved by miniaturizing transistors. However, the miniaturization of transistors seems to have approached the limit thereof. There are concerns that, even if transistors are made even smaller, the transistors would not work properly due to short-channel effects and the like.
To solve the above problem fundamentally, a method of a three-dimensional process of a semiconductor substrate to form three-dimensional transistors is proposed. A three-dimensional transistor (referred to as a pillar transistor, hereinafter) of a type that uses a silicon pillar that extends in a direction perpendicular to a main surface of a semiconductor substrate as a channel has the following advantages, among other things: the main surface of the semiconductor substrate is less occupied, and large drain current is obtained due to full depletion. Therefore, it is possible to improve the integration degree of semiconductor integrated circuits (See Japanese Patent Application Laid-Open No. 2010-80756, Japanese Patent Application Laid-Open No. 2008-205483, and Japanese Patent Application Laid-Open No. 2008-177565, for example).
Conventionally, when transistors that make up a semiconductor device are laid out, the automatic placement and routing of cells, which are made up of the transistors, is carried out by automatic layout tool. In general, during the automatic placement and routing of cells, in order to place a cell, a placement area called cell row is set up: the height and width of the placement area are constant. For example, FIGS. 7A and 7b are a diagram showing cell rows that are disposed in a peripheral circuit section around array sections that are made up of memory cells in a semiconductor memory device. As shown in FIG. 7A, while the array sections 300 are made up of memory cells, the cell rows 100 are disposed in the peripheral circuit section 200. In FIG. 7B, on the cell rows 100, cells 150, which are made up of transistors, are disposed.
FIGS. 8A and 8B are a diagram illustrating the division of a MOS (Metal Oxide Semiconductor) transistor corresponding to height H of a cell row 100 in a conventional placement and routing process. Assume that, in the following description, the channel length of the gate of the MOS transistor is constant. In this case, the division means dividing a transistor in planar view on a main surface of a semiconductor substrate.
The following takes a look at how a MOS transistor is divided when the gate width W of the MOS transistor of a cell 150 is 7 μm as shown in FIG. 8A, for example.
When the height H of a cell row 100 shown in FIGS. 7A and 7B is 4 μm, the MOS transistor is divided into two as shown in FIG. 8B so that the cell height, or the gate width W of the MOS transistors, equally becomes 3.5 p.m.
When the height H of a cell row 100 shown in FIGS. 7A and 7B is 3 μm, the MOS transistor is divided into three as shown in FIG. 8B so that the gate width W of the MOS transistors equally becomes 2.3 μm.
Meanwhile, as for a MOS transistor of a pillar type, the channel length is determined based on the depth of a pillar, and the gate width is determined based on the diameter of the pillar.
Accordingly, with respect to the height of a cell row, the number of pillar's transistors disposed is restricted. When a MOS transistor of a pillar type is divided, the division is carried out on the basis of the gate width of a unit pillar transistor; the diameter of the unit pillar transistor is changed so as not to contain fractions after the decimal point.
However, when a MOS transistor of a pillar type is used, in order to maintain the processing accuracy of a process of forming a pillar, a unit pillar transistor (one pillar-type MOS transistor) whose pillar is constant in depth and diameter is used; the unit pillar transistors, the number of which is an integer, are combined to form the MOS transistors with a desired capability. Therefore, it is not realistic to change the diameter of the pillar.
If the diameter of the pillar is changed, a process of forming a pillar for each size of diameter needs to be carried out in order to accurately fabricate the diameter of the pillar-type MOS transistor. As a result, the manufacturing processes need to be changed significantly.